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RM0008
Table 5.
Memory and bus architecture
Flash module organization (connectivity line devices)
Block
Main memory
Name
Page 0
Page 1
Page 2
Page 3
.
.
.
Page 127
System memory
Base addresses
0x0800 0000 - 0x0800 07FF
0x0800 0800 - 0x0800 0FFF
0x0800 1000 - 0x0800 17FF
0x0800 1800 - 0x0800 1FFF
.
.
.
0x0803 F800 - 0x0803 FFFF
0x1FFF B000 - 0x1FFF F7FF
Size (bytes)
2 Kbytes
2 Kbytes
2 Kbytes
2 Kbytes
.
.
.
2 Kbytes
18 Kbytes
Information block
Option Bytes
FLASH_ACR
FLASH_KEYR
FLASH_OPTKEYR
0x1FFF F800 - 0x1FFF F80F
0x4002 2000 - 0x4002 2003
0x4002 2004 - 0x4002 2007
0x4002 2008 - 0x4002 200B
16
4
4
4
Flash memory
interface
registers
FLASH_SR
FLASH_CR
FLASH_AR
Reserved
FLASH_OBR
FLASH_WRPR
0x4002 200C - 0x4002 200F
0x4002 2010 - 0x4002 2013
0x4002 2014 - 0x4002 2017
0x4002 2018 - 0x4002 201B
0x4002 201C - 0x4002 201F
0x4002 2020 - 0x4002 2023
4
4
4
4
4
4
Note:
For further information on the Flash memory interface registers, please refer to the
STM32F10xxx Flash programming manual.
Reading the Flash memory
Flash memory instructions and data access are performed through the AHB bus. The
prefetch block is used for instruction fetches through the ICode bus. Arbitration is performed
in the Flash memory interface, and priority is given to data access on the DCode bus.
Read accesses can be performed with the following configuration options:
●
●
●
Latency: number of wait states for a read operation programmed on-the-fly
Prefetch buffer (2 x 64-bit blocks): it is enabled after reset; a whole block can be
replaced with a single read from the Flash memory as the size of the block matches the
bandwidth of the Flash memory. Thanks to the prefetch buffer, faster CPU execution is
possible as the CPU fetches one word at a time with the next word readily available in
the prefetch buffer
Half cycle: for power optimization
Doc ID 13902 Rev 9
47/995
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